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PRELIMINARY PRODUCT SPECIFICATION
1
Z86L04/L08
Z8 8-BIT COST-EFFECTIVE MICROCONTROLLERS
FEATURES
Device Z86L04 Z86L08 ROM (KB) 1K 2K RAM* Speed Auto Permanent (Bytes) (MHz) Latch WDT 125 125 8 8 Optional Optional Optional Optional
s
1
Note: *General-Purpose s s s s s
18-Pin DIP and SOIC Packages 0 C to + 70 C Standard Temperature 2.0V to 3.9V Operating Range 14 Input / Output Lines Five Vectored, Prioritized Interrupts from Five Different Sources Two On-Board Comparators Software Enabled Watch-Dog Timer (WDT) Programmable Interrupt Polarity Two Standby Modes: STOP and HALT Low-Voltage Protection
s
ROM Mask/OTP Options: - ROM Protect - Auto Latch Disable - Permanent Watch-Dog Timer (WDT) - RC Oscillator - 32 kHz Crystal Operation - Low EMI - WDT Clock Source (Z86L04 only) Two Programmable 8-Bit Counter/Timers with 6-Bit Programmable Prescalers Power-On Reset (POR) Timer On-Chip Oscillator that Accepts RC, Crystal, Ceramic Resonator, LC, or External Clock Drive Clock-Free WDT Reset Low-Power Consumption (40 mw) Fast Instruction Pointer (1.5 s @ 8 MHz) Fourteen Digital Inputs at CMOS Levels; Schmitt-Triggered
s s
s s s s s
s s s s
GENERAL DESCRIPTION
Zilog's Z86L04/L08 microcontrollers (MCUs) are members of the Z8 single-chip MCU family, which offer easy software/hardware system expansion. For applications demanding powerful I/O capabilities, the MCU's dedicated input and output lines are grouped into three ports, and are configurable under software control to provide timing, status signals, or parallel I/O. One on-chip counter/timer, with a large number of user-selectable modes, off-load the system of administering realtime tasks such as counting/timing and I/O data communications. Additionally, two on-board comparators process analog signals with a common reference voltage (Figure 1).
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GENERAL DESCRIPTION (Continued)
Note: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground
Input Vcc GND XTAL
Circuit VCC GND
Device VDD VSS
Port 3
Machine Timing & Inst. Control
Counter/ Timer
ALU
Interrupt Control
FLAG
Program Memory
Two Analog Comparators
Register Pointer General-Purpose Register File
Program Counter
Port 2
Port 0
I/O (Bit Programmable)
I/O
Figure 1. Z86L04/L08 Functional Block Diagram
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Z86L04/L08 Z8 8-Bit Cost-Effective Microcontrollers
D7-D0 Z8 MCU
A10-A0
1
Data MUX Z8 PORT2 D7-D0 /OE P31
Address MUX
A10-A0
Address Counter
A10-A0
EPROM D7-D0 Option Bits
3 Bits PGM Mode Logic
Clear Clock P00 P01
EPM /CE /PGM P32 XT1 P02
VPP P33
Figure 2. EPROM Programming Mode Block Diagram
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PIN DESCRIPTIONS
P24 P25 P26 P27 VCC XTAL2 XTAL1 P31 P32
1
18
DIP 18 - Pin
9
10
P23 P22 P21 P20 GND P02 P01 P00 P33
P24 P25 P26 P27 VCC XTAL2 XTAL1 P31 P32
1
18
SOIC 18 - Pin
9
10
P23 P22 P21 P20 GND P02 P01 P00 P33
Figure 4. 18-Pin SOIC Configuration Figure 3. 18-Pin Standard Mode Configuration Table 1. 18-Pin Standard Mode Identification Pin # 1-4 5 6 7 8 9 10 11-13 14 15-18 Symbol P24-P27 VCC XTAL2 XTAL1 P31 P32 P33 P00-P02 GND P20-P23 Function Direction Pin # 1-4 5 6 7 8 9 10 11-13 14 15-18 Table 2. 18-Pin SOIC Pin Identification Symbol P24-P27 VCC XTAL2 XTAL1 P31 P32 P33 P00-P02 GND P20-P23 Function Direction
Port 2, Pins 4, 5, 6, 7In/Output Power Supply Crystal Oscillator Output Clock Crystal Oscillator Input Clock Port 3, Pin 1, AN1 Input Port 3, Pin 2, AN2 Input Port 3, Pin 3, REF Input Port 0, Pins 0, 1, 2 In/Output Ground Port 2, Pins 0, 1, 2, 3In/Output
Port 2, Pins 4,5,6,7 In/Output Power Supply Crystal Osc. Clock Crystal Osc. Clock Port 3, Pin 1, AN1 Port 3, Pin 2, AN2 Port 3, Pin 3, REF Port 0, Pins 0,1,2 Ground Port 2, Pins 0,1,2,3 Output Input Input Input Input In/Output In/Output
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Z86L04/L08 Z8 8-Bit Cost-Effective Microcontrollers
ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to VSS [Note 1] Voltage on VDD Pin with Respect to VSS Voltage on Pin 7 with Respect to VSS [Note 2] (Z86C02/L02) Voltage on Pin 7,8,9,10 with Respect to VSS [Note 2] (Z86E02) Total Power Dissipation Maximum Allowed Current out of VSS Maximum Allowed Current into VDD Maximum Allowed Current into an Input Pin [Note 3] Maximum Allowed Current into an Open-Drain Pin [Note 4] Maximum Allowed Output Current Sinked by Any I/O Pin Maximum Allowed Output Current Sourced by Any I/O Pin Maximum Allowed Output Current Sinked by Port 2, Port 0 Maximum Allowed Output Current Sourced by Port 2, Port 0 Notes: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Total power dissipation should not exceed 462 mW for the package. Power dissipation is calculated as follows: Total Power dissipation = VDD x [I DD - (sum of IOH)] + sum of [(V DD - VOH) x IOH] + sum of (V 0L x I0L) -600 -600 Min -40 -65 -0.7 -0.3 -0.7 -0.7 Max +105 +150 +12 +7 V DD+1 V DD+1 462 300 270 +600 +600 20 20 80 80 Units C C V V V V mW mA mA A A mA mA mA mA
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1. This applies to all pins except where otherwise noted. 2. Maximum current into pin must be 600 A. There is no input protection diode from pin to VDD. 3. This excludes Pin 6 and Pin 7. 4. Device pin is not at an output Low state.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Figure 5).
From Output Under Test
150 pF
Figure 5. Test Load Diagram
Capacitance
TA = 25C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND. Parameter Input capacitance Output capacitance I/O capacitance DS97LVO0901 Min 0 0 0 Max 15 pF 20 pF 25 pF PRELIMINARY 5
Z86L04/L08 Z8 8-Bit Cost-Effective Microcontrollers
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DC CHARACTERISTICS Z86L04/L08
VCC [3] 2.0V 3.9V VCL Clock Input Low Voltage 2.0V 3.9V VIH VIL VOH VOL1 VOL2 Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Low Voltage 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V VOFFSET Comparator Input Offset Voltage VLV IIL VCC Low Voltage Auto Reset Input Leakage (Input Bias Current of Comparator) Output Leakage Comparator Input Common Mode Voltage Range 2.0V 3.9V 1.4 2.0V 3.9V 2.0V 3.9V VICR 2.0 3.9 -1.0 -1.0 -1.0 -1.0 0 0 TA = 0 C to +70 C Min Max 0.9 VCC VCC+0.3 0.9 VCC VSS-0.3 VSS-0.3 0.9 VCC 0.9 VCC VSS-0.3 VSS-0.3 VCC-0.4 VCC-0.4 0.8 0.4 1.0 0.8 25 25 2.15 1.0 1.0 1.0 1.0 VCC -1.0 VCC -1.0 VCC+0.3 0.1 VCC 0.1 VCC VCC+0.3 VCC+0.3 0.1 VCC 0.1 VCC 3.0 3.0 0.2 0.1 0.8 0.3 10 10 Typical @ 25 C
Sym. VCH
Parameter Clock Input High Voltage
Units Conditions V Driven by External Clock Generator V Driven by External Clock Generator V Driven by External Clock Generator V Driven by External Clock Generator V V V V V V V V V V mV mV V A A A A V V VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC IOH = - 500 A IOH = - 500 A IOL = +1.0 mA IOL = +1.0 mA IOL = + 3.0 mA IOL = + 3.0 mA
Notes
1 1 1 1 4,5 4,5 4,5 4,5 4,5 4,5
IOL
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Z86L04/L08 Z8 8-Bit Cost-Effective Microcontrollers TA = 0 C to +70 C Typical Min Max @ 25 C 3.3 6.8 6.0 9.0 2.3 3.8 3.8 4.8 10 10 12 32 -8 -16
Sym Parameter ICC Supply Current
VCC [3] 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V
Units mA mA mA mA mA mA mA mA A A A A A A
Conditions @ 2 MHz @ 2 MHz @ 8 MHz @ 8 MHz @ 2 MHz @ 2 MHz @ 8 MHz @ 8 MHz
Notes 5,6 5,6 5,6 5,6 5,6,7 5,6,7 5,6,7 5,6,7 6,7 6,7
1
ICC1 Standby Current (Halt Mode)
ICC2 Standby Current (Stop Mode) IALL Auto Latch Low Current
1.0 1.0 3.0 16 -1.5 -8.0
0V < VIN < VCC 0V < VIN < VCC 0V < VIN < VCC
IALH Auto Latch High Current
Notes: 1. Port 0, 2, and 3 only. 2. VSS = 0V = GND. The device operates down to V LV. The minimum operational VCC is determined by the value of the voltage VLV at the ambient temperature. 3. VCC = 2.0V to 3.9V, typical values measured at VCC = 3.3 V. 4. Standard Mode (not Low EMI mode). 5. Inputs at VCC or VSS, outputs are unloaded. 6. WDT is not running. 7. Comparator inputs at VCC.
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AC ELECTRICAL CHARACTERISTICS
1
3
Clock
2 7 7 2 3
T
IN
4 6 5
IRQ
N
8 9
Figure 6. AC Electrical Timing Diagram
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AC ELECTRICAL CHARACTERISTICS Timing Table (Standard Mode for SCLK/TCLK = XTAL/2)
TA= 0 C to +70 C 8 MHz No. 1 2 3 4 5 6 7 8 9 10 11 Symbol TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin, TtTin TwIL TwIH Twdt Tpor Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise and Fall Time Int. Request Input Low Time Int. Request Input High Time Watch-Dog Timer Delay Time Before Time-Out Power-On Reset Time VCC 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V .39V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 3.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V Min 125 125 Max DC DC 25 25 Units ns ns ns ns ns ns ns ns Notes 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1,2,3 1,2,3 1,2,3 1,2,3
1
62 62 70 70 5TpC 5TpC 8TpC 8TpC 100 100 70 70 5TpC 5TpC 25 10 70 50 20 6
ns ns ns ns
ms ms ms ms ms ms
4 4 5 5
Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 3. IRQ 0,1,2 only. 4. For Z86L08 using internal RC oscillator. 5. For Z86L04 using internal RC oscillator. Precaution: Maximum frequency in Low EMI mode is 1 MHz.
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PIN FUNCTIONS
XTAL1, XTAL2 Crystal In, Crystal Out (time-based input and output, respectively). These pins connect a parallelresonant crystal, LC, RC, or an external single-phase clock (8 MHz max) to the on-chip clock oscillator and buffer. Port 0, P02-P00. Port 0 is a 3-bit bidirectional, Schmitt-triggered CMOS compatible I/O port. These three I/O lines can be globally configured under software control to be inputs or outputs (Figure 7). Auto Latch. The Auto Latch puts valid CMOS levels on all CMOS inputs (except P33, P32, P31) that are not externally driven. A valid CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer. On Power-up and Reset, the Auto Latch will set the ports to an undetermined state of 0 or 1. Default condition is Auto Latches enabled.
Z8
Port 0 (I/O)
Open
PAD
Out
In
Auto Latch Option
R
500 k
Figure 7. Port 0 Configuration
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Zilog Port 2, P27-P20. Port 2 is an 8-bit, bit-programmable, bidirectional, Schmitt-triggered, CMOS, compatible I/O port. These eight I/O lines can be configured under software
Z86L04/L08 Z8 8-Bit Cost-Effective Microcontrollers control to be inputs or outputs, independently. Bits programmed as outputs can be globally programmed as either push-pull or open-drain (Figure 8).
1
Z8 Port 2 (I/O)
Port 2
Open-Drain Open PAD
Out 1.5 In 2.3 Hysteresis
VCC @ 5.0V
Auto Latch Option R 500 k
Figure 8. Port 2 Configuration
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PIN FUNCTIONS (Continued)
Port 3, P33-P31. Port 3 is a 3-bit, CMOS, compatible port with three fixed input (P33-P31) lines. These three input lines can be configured under software control as digital Schmitt-trigger inputs or analog inputs. These three input lines are also used as the interrupt sources IRQ0-IRQ3 and as the timer input signal TIN (Figure 9).
Z8 Port 3
R247 = P3M
0 = Digital 1 = Analog D1
TIN
DIG. PAD P31 (AN1)
P31 Data Latch IRQ2
+
AN.
IRQ3
PAD P32 (AN2) PAD
P32 Data Latch + P33 (REF)
IRQ0
P33 Data Latch Vcc IRQ1
IRQ 0,1,2 = Falling Edge Detection IRQ3 = Rising Edge Detection
Figure 9. Port 3 Configuration
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Zilog Comparator Inputs. Two analog comparators are added to input of Port 3, P31 and P32, for interface flexibility. The comparators reference voltage P33 (REF) is common to both comparators. Typical applications for the on-board comparators; Zero crossing detection, A/D conversion, voltage scaling, and threshold detection. In analog mode, P33 input functions serve as a reference voltage to the comparators.
Z86L04/L08 Z8 8-Bit Cost-Effective Microcontrollers The dual comparator (common inverting terminal) features a single power supply which discontinues power in STOP mode. The common voltage range is 0-4V when the VCC is 5.0V; the power supply and common mode rejection ratios are 90 dB and 60 dB, respectively. Interrupts are generated on either edge of Comparator 2's output, or on the falling edge of Comparator 1's output. The comparator output is used for interrupt generation, Port 3 data inputs, or TIN through P31. Alternatively, the comparators can be disabled, freeing the reference input (P33) for use as IRQ1 and/or P33 input.
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FUNCTIONAL DESCRIPTION
The following special functions have been incorporated into the Z86L04/L08 devices to enhance the standard Z8 core architecture to provide the user with increased design flexibility. RESET. This function is accomplished by means of a Power-On Reset or a Watch-Dog Timer Reset. Upon powerup, the Power-On Reset circuit waits for TPOR ms, plus 18 clock cycles, then starts program execution at address 000C (Hex) (Figure 10). The control registers' reset values are shown in Table 3.
XTAL OSC
INT OSC POR (Cold Start) Delay Line TPOR ms P27 (Stop Mode)
18 CLK Reset Filter
Chip Reset
Figure 10. Internal Reset Configuration
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Z86L04/L08 Z8 8-Bit Cost-Effective Microcontrollers Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is used for a POR timer function. The POR time allows VCC and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of the five following conditions:
s s s s s
Zilog Table 3. Control Register Reset Values Reset Condition Addr Reg. FF FE FD FC FB FA SPL GPR RP FLAGS IMR IRQ D7 D6 D5 D4 D3 D2 D1 D0 Comments 00000000 00000000 00000000 UUUUUUUU 0UUUUUUU U U 0 0 0 0 0 0 IRQ3 is used for positive edge detection UUUUUUUU UUU0UU01 U U U U U U 0 0 P2 open-drain 1 1 1 1 1 1 1 1 Inputs after reset UUUUUUU0 UUUUUUUU UUUUUU00 UUUUUUUU 00000000
Power bad to power good status Stop-Mode Recovery WDT time-out WDT time-out (in HALT Mode) WDT time-out (in STOP Mode)
Watch-Dog Timer Reset. The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT is initially enabled by executing the WDT instruction and is retriggered on subsequent execution of the WDT instruction. The timer circuit is driven by an onboard RC oscillator. If the permanent WDT option is selected then the WDT is enabled after reset and operates in RUN Mode, HALT mode, STOP mode and cannot be disabled. If the permanent WDT option is not selected then the WDT, when enabled by the user's software, does not operate in STOP Mode, but it can operate in HALT Mode by using a WDH instruction.
F9 F8* F7* F6* F5 F4 F3 F2 F1
IPR P01M P3M P2M PRE0 T0 PRE1 T1 TMR
Notes: *Registers are not reset after a STOP-Mode Recovery using P27 pin. A subsequent reset will cause these control registers to be reconfigured as shown in Table 4 and the user must avoid bus contention on the port pins or it may affect device reliability.
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Zilog Program Memory. The Z8 addresses up to 1024,2048 bytes of internal program memory (Figure 11). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts. Bytes 0-1023/0-2047 are on-chip mask programmable ROM.
Z86L04/L08 Z8 8-Bit Cost-Effective Microcontrollers
Location 255 254 253 252 Stack Pointer (Bits 7-0) General Purpose GPR Register Pointer Program Control Flags Interrupt Mask Register Interrupt Request Register Interrupt Priority Register Ports 0-1 Mode Port 3 Mode Port 2 Mode T Prescaler o Timer/Counter0 T1 Prescaler Timer/Counter1 Timer Mode Not Implemented
Indentifiers SPL
1
RP Flags IMR IRQ IPR P01M P3M P2M PRE0 T0 PRE1 T1 TMR
1024/2047 Location of First Byte of Instruction Executed After RESET On-Chip ROM 12 11 10 9 8 Interrupt Vector (Lower Byte) 7 6 5 Interrupt Vector (Upper Byte) 4 3 2 1 0 IRQ5 IRQ5 IRQ4 IRQ4 IRQ3 IRQ3
251 250 249 248 247 246 245 244 243 242 241 240
IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0
128 127 General Purpose Registers 4 3 2 1 0 Port 3 Port 2 Reserved Port 0 P3 P2 P1 P0
Figure 11. Program Memory Map Register File. The Register File consists of three I/O port registers, 61 general-purpose registers, and 12 control and status registers R0-R3, R4-R127 and R241-R255, respectively (Figure 12). General-purpose registers occupy the 04H to 7FH address space. I/O ports are mapped as per the existing CMOS Z8. The instructions can access registers directly or indirectly through an 8-bit address field. This allows short 4-bit register addressing using the Register Pointer. In the 4-bit mode, the register file is divided into eight working register groups, each occupying 16 continuous locations. The Register Pointer (Figure 13) addresses the starting location of the active working-register group.
Figure 12. Register File
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FUNCTIONAL DESCRIPTION (Continued)
General-Purpose Registers (GPR). These registers are undefined after the device is powered up. The registers keep their last value after any reset, as long as the reset occurs in the VCC voltage-specified operating range. Note: Register R254 has been designated as a general-purpose register. But is set to 00Hex after any reset. Counter/Timer. There are two 8-bit programmable counter/timers (T0 and T1), each driven by its 6-bit programmable prescaler. The T1 prescaler is driven by internal or external clock sources. (Figure 14). The 6-bit prescaler divide the input frequency of the clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. When both counter and prescaler reach the end of count, a timer interrupt request IRQ5 (T1 or IRQ4 (T0) is generated.
The lower nibble of the register file address provided by the instruction points to the specified register.
r7 r6
r5 r4
r3 r2
r1 r0
R253 (Register Pointer)
The upper nibble of the register file address provided by the register pointer specifies the active working-register group.
FF
Register Group F
F0
R15 to R0
7F 70 6F 60 5F 50 4F 40 3F 30 2F 20 1F
Specified Working Register Group
The counter can be programmed to start, stop, restart to continue, or restart from the initial value. The counters are also programmed to stop upon reaching zero (Single-Pass mode) or to automatically reload the initial value and continue counting (Modulo-N Continuous Mode). The counters, but not the prescaler, are read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and is either the internal microprocessor clock divided by four, or an external signal input through Port 3. The Timer Mode register configures the external timer input (P31) as an external clock, a trigger input that is retriggerable or non-retriggerable, or used as a gate input for the internal clock.
Register Group 1
10 0F
R15 to R0 R15 to R4 R3 to R0
Register Group 0 I/O Ports
00
Figure 13. Register Pointer Stack Pointer. The Z8 has an 8-bit Stack Pointer (R255) used for the internal stack that resides within the 60 general-purpose registers. It is set to 00Hex after any reset.
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Z86L04/L08 Z8 8-Bit Cost-Effective Microcontrollers
Internal Data Bus Write OSC PRE0 Initial Value Register Write T0 Initial Value Register Read T0 Current Value Register
1
/2 /4 Internal Clock 6-Bit Down Counter 8-bit Down Counter
IRQ4
External Clock
Clock Logic /4
6-Bit Down Counter
8-Bit Down Counter
IRQ5
Internal Clock Gated Clock Triggered Clock
PRE1 Initial Value Register Write Write
T1 Initial Value Register Read Internal Data Bus
T1 Current Value Register
TIN P31
Figure 14. Counter/Timers Block Diagram
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FUNCTIONAL DESCRIPTION (Continued)
Interrupts. The Z8 has five interrupts from four different sources. These interrupts are maskable and prioritized (Figure 15). The sources are divided as follows: the falling edge of P31 (AN1), P32 (AN2), P33 (REF), the rising edge of P32 (AN2), and one counter/timer. The Interrupt Mask Register globally or individually enables or disables the five interrupt requests (Table 4). When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register. All Z8 interrupts are vectored through locations in program memory. When an Interrupt machine cycle is activated, an Interrupt Request is granted. This disables all subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt. This memory location and the next byte contain the 16-bit starting address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests needs service. User must select any Z86E08 mode in Zilog's C12 ICEBOXTM emulator. The rising edge interrupt is not directly supported on the Z86CCP00ZEM emulator. Table 4. Interrupt Types, Sources, and Vectors Vector Location 0,1 2,3 4,5 6,7 8,9 10,11
Name IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5
Source AN2(P32) REF(P33) AN1(P31) AN2(P32) T0 T1
Comments External (F)Edge External (F)Edge External (F)Edge External (R)Edge Internal Internal
Note: F = Falling edge triggered R = Rising edge triggered
IRQ0 - IRQ5
IRQ
IMR 6 IPR
Global Interrupt Enable Interrupt Request
Priority Logic
Vector Select
Figure 15. Interrupt Block Diagram
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Zilog Clock. The Z8 on-chip oscillator has a high-gain, parallelresonant amplifier for connection to a crystal, ceramic resonator, or any suitable external clock source (XTAL1 = INPUT, XTAL2 = OUTPUT). The crystal should be AT cut, 8 MHz max, with a series resistance (RS) of less than or equal to 100 Ohms.
Z86L04/L08 Z8 8-Bit Cost-Effective Microcontrollers The crystal or ceramic resonator should be connected across XTAL1 and XTAL2 using the vendors crystal or ceramic resonator recommended capacitors from each pin directly to device ground pin 14 (Figure 16). Note that the crystal capacitor loads should be connected to VSS, Pin 14 to reduce Ground noise injection.
1
XTAL1 C1 C1
XTAL1
XTAL1 C R
XTAL1
*
XTAL2 C2
Vss *
*
C2
Vss *
L
Vss *
XTAL2
XTAL2
XTAL2
Ceramic Resonator or Crystal
LC Clock
External Clock
RC Clock
* =Device Ground Pin
Note: If 32 KHz oscillator is selected then an external 10 Megohm resistor must be connected between XTAL1 and XTAL2 pins.
Figure 16. Oscillator Configuration
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FUNCTIONAL DESCRIPTION (Continued)
HALT Mode. This instruction turns off the internal CPU clock but not the crystal oscillation. The counter/timer and external interrupts IRQ0, IRQ1, IRQ2 and IRQ3 remain active. The device is recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction after the HALT. STOP Mode. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 A. The STOP mode is released by a RESET through a Stop-Mode Recovery (pin P27). A Low condition on pin P27 releases the STOP mode even if P27 is an output. Program execution begins at location 000C(Hex). However, when P27 is used to release the STOP mode, the I/O port mode registers are not reconfigured to their default power-on conditions. This prevents any I/O, configured as output when the STOP instruction was executed, from glitching to an unknown state. To use the P27 release approach with STOP mode, use the following instruction: LD NOP STOP P2M, #1XXX XXXXB Watch-Dog Timer (WDT). The Watch-Dog Timer is enabled by instruction WDT. When the WDT is enabled, it cannot be stopped by the instruction. With the WDT instruction, the WDT is refreshed when it is enabled within every 1 Twdt period; otherwise, the controller resets itself, The WDT instruction affects the flags accordingly; Z=1, S=0, V=0. WDT = 5F (Hex) Opcode WDT (5FH). The first time opcode 5FH is executed, the WDT is enabled and subsequent execution clears the WDT counter. This must be done at least every TWDT; otherwise, the WDT times out and generates a reset. The generated reset is the same as a power-on reset of TPOR, plus 18 XTAL clock cycles. The internal RC driven WDT does not run in stop mode, unless the permanent WDT enable option is selected. The WDT does not run in halt mode unless WDH instruction is executed or permanent WDT enable option is selected. Opcode WDH (4FH). When this instruction is executed it enables the WDT during HALT. If not, the WDT stops when entering HALT. This instruction does not clear the counters, it just makes it possible to have the WDT running during HALT mode. A WDH instruction executed without executing WDT (5FH) has no effect. Note: Opcode WDH and permanently enabled WDT is not directly supported by the Z86CCP00ZEM. WDT Clock Source. The WDT clock source option selects the clock source for the WDT. It can be the internal onboard RC oscillator or the internal system clock (SCLK). If the SCLK is selected, then the WDT time out (TWDT) is 130,416 x SCLK and the TPOR is 16,362 x SCLK. Also, if the permanent WDT option is selected in this case; the WDT will not run in STOP mode. (Z86L04 only) Auto Reset Voltage (VLV). The Z8 has an auto-reset builtin. The auto-reset circuit resets the Z8 when it detects the VCC below VLV. Figure 17 shows the Auto Reset Voltage versus temperature.
Notes: X = Dependent on user's application. Stop-Mode Recovery pin P27 is not edge triggered.
In order to enter STOP or HALT mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user executes a NOP (opcode=FFH) immediately before the appropriate SLEEP instruction, such as: FF 6F or FF 7F NOP STOP NOP HALT ; clear the pipeline ; enter STOP mode ; clear the pipeline ; enter HALT mode
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Z86L04/L08 Z8 8-Bit Cost-Effective Microcontrollers
Vcc (Volts) 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 -40C -20C 0C 20C 40C 60C 80C 100C Temp
1
Figure 17. Typical Auto Reset Voltage (VLV) vs. Temperature
OPTIONS
ROM protect, Low Noise, Auto Latch Disable, RC Oscillator, 32 kHz Crystal and Permanent WDT enable features as options and must be selected at the time of ROM code submissions. ROM Protect. ROM Protect fully protects the Z8 ROM code from being read externally. When ROM Protect is selected, the instructions LDC and LDCI are supported. (However, instructions LDE and LDEI are not supported.) Auto Latch Disable. Auto Latch Disable option when Selected will globally disable all Auto Latches. RC. RC Oscillator option when selected will allow using a resistor (R) and a capacitor (C) as a clock source. WDT Clock Source. This selects the clock source of the WDT and POR counter chain to be driven by either the internal system clock or the internal on-board RC oscillator. (Z86L04 only). Low EMI. The Low EMI (Low noise) mode by passes the divide by two clock circuit (SCLK = XTAL/1) and lowers the output sink and drive currents by 75 percent. The maximum oscillator frequency at XTAL pins is 1MHz. WDT Enable. WDT Enable option bit when selected will have the WDT permanently enabled in all modes and can not be stopped in HALT or STOP Mode, if the internal RC oscillator is selected as the clock source. If the system clock (SCLK) is the clock source, the WDT will be stopped in STOP mode. Please note that when using the device in a noisy environment, it is suggested that the voltages on the EPM and CE pins be clamped to VCC through a diode to VCC to prevent accidentally entering the OTP mode. The VPP requires both a diode and a 100 pF capacitor. 32 kHz Crystal. This disables the internal feedback resistor on the crystal oscillator circuit (not for RC oscillator circuit) so that a 32 kHz crystal can be connected to the XTAL1 and XTAL2 pins.
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Z8 CONTROL REGISTERS
R241 TMR D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) 0 Disable T0 Count 1 Enable T0 Count 0 No Function 1 Load T 1 0 Disable T 1 Count 1 Enable T 1 Count T IN 00 01 10 Modes External Clock Input Gate Input Trigger Input (Non-retriggerable) 11 Trigger Input (Retriggerable) Reserved (Must be 0.) R247 P3M D7 D6 D5 D4 D3 D2 D1 D0
0 Port 2 Open-Drain 1 Port 2 Push-pull Port 3 Inputs 0 Digital Mode 1 Analog Mode Reserved (Must be 0)
Figure 22. Port 3 Mode Register (F7H: Write Only)
R248 P01M D7 D6 D5 D4 D3 D2 D1 D0
Figure 18. Timer Mode Register (F1H: Read/Write)
P03-P00 Mode 00 = Output 01 = Input Reserved (Must be 1.) Reserved (Must be 0.)
R242 T1 D7 D6 D5 D4 D3 D2 D1 D0
Figure 23. Port 0 and 1 Mode Register (F8H: Write Only)
R249 IPR
T1 Initial Value (When Written) (Range 1-256 Decimal 01-00 HEX) T1 Current Value (When READ)
D7 D6 D5 D4 D3 D2 D1 D0
Figure 19. Counter Timer 1 Register (f2H:Read/Write)
Interrupt Group Priority 000 Reserved 001 C > A > B 010 A > B > C 011 A > C > B 100 B > C > A 101 C > B > A 110 B > A > C 111 Reserved IRQ1, IRQ4 Priority (Group C) 0 IRQ1 > IRQ4 1 IRQ4 > IRQ1 IRQ0, IRQ2 Priority (Group B) 0 IRQ2 > IRQ0 1 IRQ0 > IRQ2 IRQ3, IRQ5 Priority (Group A) 0 IRQ5 > IRQ3 1 IRQ3 > IRQ5 Reserved (Must be 0.)
R243 PRE1 D7 D6 D5 D4 D3 D2 D1 D0
Count Mode 0 T 1 Single Pass 1 T 1 Modulo Clock Source 1 T 1 Internal 0 T 1 External Timing Input (T IN) Mode Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX)
Figure 24. Interrupt Priority Register (F9H: Write Only)
Figure 20. Prescaler1 Register (F3H: Write Only)
R246 P2M D7 D6 D5 D4 D3 D2 D1 D0
P2 7 - P2 0 I/O Definition 0 Defines Bit as OUTPUT 1 Defines Bit as INPUT
Figure 21. Port 2 Mode Register (F6H: Write Only) 22 PRELIMINARY DS97LVO0901
Zilog
R250 IRQ D7 D6 D5 D4 D3 D2 D1 D0 IRQ0 = P32 Input IRQ1 = P33 Input IRQ2 = P31 Input IRQ3 = P32 Input IRQ4 = Reserved IRQ5 = T1 Reserved (Must be 0.) R253 RP
Z86L04/L08 Z8 8-Bit Cost-Effective Microcontrollers
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0.) Register Pointer
1
Figure 28. Register Pointer FDH: Read/Write)
R255 SPL
Figure 25. Interrupt Request Register (FAH: Read/Write)
D7
D6 D5 D4 D3 D2 D1 D0
Stack Pointer Lower Byte (SP 0 - SP 7 )
R251 IMR D7 D6 D5 D4 D3 D2 D1 D0
Figure 29. Stack Pointer (FFH: Read/Write)
1 Enables IRQ5-IRQ0 (D = IRQ0) 0 Reserved (Must be 0.) 1 Enables Interrupts
Figure 26. Interrupt Mask Register (FBH: Read/Write)
R252 Flags D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1 User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag
Figure 27. Flag Register (FCH: Read/Write)
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PACKAGE INFORMATION
Figure 30. 18-Pin DIP Package Diagram
Figure 31. 18-Pin SOIC Package Diagram
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Z86L04/L08 Z8 8-Bit Cost-Effective Microcontrollers
ORDERING INFORMATION
Standard Temperature 18-Pin DIP Z86L0408PSC Z86L0808PSC 18-Pin SOIC Z86L0408SSC Z86L0808SSC
1
For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired.
CODES Preferred Package
P = Plastic DIP
Speed
08 = 8 MHz
Longer Lead Time
S = SOIC
Environmental
C = Plastic Standard
Preferred Temperature
S = 0 C to +70 C
Example: Z 86L08 08 P S C
is a Z86L08, 08 MHz, Plastic DIP, 0 C to +70 C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix
(c) 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com
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Z86L04/L08 Z8 8-Bit Cost-Effective Microcontrollers
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DS97LVO0901

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